04321nam a22004575i 4500001001800000003000900018005001700027007001500044008004100059020001800100020001900118024003100137040000900168082001400177100003100191245031600222264003800538300003200576336002600608337002600634338003900660347002400699490008000723505138100803520109802184650002203282650003603304650002503340650002203365650006203387650002603449700002803475700003303503700003003536700002803566710003403594773002003628776003603648830008003684856009903764978-0-387-33403-5DE-He21320260521091903.0cr nn 008mamaa100301s2006    xxu|    s    |||| 0|eng d  a9780387334035  a997803873340357 a10.1007/0-387-33403-32doi  cCICY04a004.62231 aGlesner, Manfred.eeditor.10aVLSI-SOC: From Systems to Chipsh[recurso electrónico] :bIFIP TC 10/ WG 10.5 Twelfth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2003), December 1-3, 2003, Darmstadt, Germany /cedited by Manfred Glesner, Ricardo Reis, Leandro Indrusiak, Vincent Mooney, Hans Eveking. 1aBoston, MA :bSpringer US,c2006.  aX, 315 p.bonline resource.  atextbtxt2rdacontent  acomputerbc2rdamedia  arecurso en líneabcr2rdacarrier  atext filebPDF2rda1 aIFIP International Federation for Information Processing,x1571-5736 ;v2000 aEffect of Power Optimizations on Soft Error Rate -- Dynamic Models for Substrate Coupling in Mixed-Mode Systems -- Hinoc: A Hierarchical Generic Approach for on-Chip Communication, Testing and Debugging of SoCs -- Automated Conversion of SystemC Fixed-Point Data Types -- Exploration of Sequential Depth by Evolutionary Algorithms -- Validation of Asynchronous Circuit Specifications Using IF/CADP -- On-Chip Property Verification Using Assertion Processors -- Run-Time FPGA Reconfiguration for Power-/Cost-Optimized Real-time Systems -- A Switched Opamp Based 10 Bits Integrated ADC for Ultra Low Power Applications -- Exploring the Capabilities of Reconfigurable Hardware for OFDM-Based Wlans -- Software-Based Test for Nonprogrammable Cores in Bus-Based System-On-Chip Architectures -- Optimizing SOC Test Resources Using Dual Sequences -- A Novel full Automatic Layout Generation Strategy for Static CMOS Circuits -- Low Power Java Processor for Embedded Applications -- Impact of Gate Leakage on Efficiency of Circuit Block Switch-Off Schemes -- Evaluation Methodology for Single Electron Encoded Threshold Logic Gates -- Asynchronous Integration of Coarse-Grained Reconfigurable XPP-Arrays Into Pipelined Risc Processor Datapath -- Gray Encoded Arithmetic Operators Applied to FFT and FIR Dedicated Datapaths -- Stuck-At-Fault Testability of SPP Three-Level Logic Forms.  aInternational Federation for Information Processing The IFIP series publishes state-of-the-art results in the sciences and technologies of information and communication. The scope of the series includes: foundations of computer science; software theory and practice; education; computer applications in technology; communication systems; systems modeling and optimization; information systems; computers and society; computer systems technology; security and protection in information processing systems; artificial intelligence; and human-computer interaction. Proceedings and post-proceedings of referred international conferences in computer science and interdisciplinary fields are featured. These results often precede journal publication and represent the most current research. The principal aim of the IFIP series is to encourage education and the dissemination and exchange of information about all aspects of computing. For more information about the 300 other books in the IFIP series, please visit www.springeronline.com. For more information about IFIP, please visit www.ifip.org. 0aCOMPUTER SCIENCE. 0aCOMPUTER NETWORK ARCHITECTURES. 0aSYSTEMS ENGINEERING.14aCOMPUTER SCIENCE.24aCOMPUTER SYSTEMS ORGANIZATION AND COMMUNICATION NETWORKS.24aCIRCUITS AND SYSTEMS.1 aReis, Ricardo.eeditor.1 aIndrusiak, Leandro.eeditor.1 aMooney, Vincent.eeditor.1 aEveking, Hans.eeditor.2 aSpringerLink (Online service)0 tSpringer eBooks08iPrinted edition:z9780387334028 0aIFIP International Federation for Information Processing,x1571-5736 ;v20040uhttp://dx.doi.org/10.1007/0-387-33403-3zVer el texto completo en las instalaciones del CICY